RFTH=ONE, TFERI=NOT_SET, TSRFULLF=NOT_SET, RFERI=NOT_SET, RSRFULLF=NOT_SET, TFTH=ONE
FIFO Control
| RCNT | Receive FIFO Count. |
| RFTH | Receive FIFO Threshold. 0 (ONE): A read data request interrupt (RDREQI) is asserted when >= 1 FIFO slot is full. 1 (TWO): A read data request interrupt (RDREQI) is asserted when >= 2 FIFO slots are full. 2 (FOUR): A read data request interrupt (RDREQI) is asserted when >= 4 FIFO slots are full. |
| RFIFOFL | Receive FIFO Flush. 1 (SET): Flush the contents of the receive FIFO and any data in the receive shift register. |
| RFERI | Receive FIFO Error Interrupt Flag. 0 (NOT_SET): A receive FIFO error has not occurred since RFERI was last cleared. 1 (SET): A receive FIFO error occurred. |
| RSRFULLF | Receive Shift Register Full . 0 (NOT_SET): The receive data shift register is not full. 1 (SET): The receive data shift register is full. |
| TCNT | Transmit FIFO Count. |
| TFTH | Transmit FIFO Threshold. 0 (ONE): A transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO slot is empty. 1 (TWO): A transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO slots are empty. 2 (FOUR): A transmit data request interrupt (TDREQI) is asserted when >= 4 FIFO slots are empty. |
| TFIFOFL | Transmit FIFO Flush. 1 (SET): Flush the contents of the transmit FIFO. If data is pending in the transmit shift register but a transmit has not begun, the shift register is also flushed. |
| TFERI | Transmit FIFO Error Interrupt Flag. 0 (NOT_SET): A transmit FIFO error has not occurred since TFERI was last cleared. 1 (SET): A transmit FIFO error occurred. |
| TSRFULLF | Transmit Shift Register Full Flag. 0 (NOT_SET): The transmit shift register is not full. 1 (SET): The transmit shift register is full. |